PUBLICATION DETAILS

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List Of Publications

Papers Published in Journals and Conferences:

Total Publications: 85

21 papers in International Refereed Journals

49 papers in International Conferences

15 papers in National Conferences

Papers Communicated to Refereed Journals and Conferences: 7

Year Wise Summary of Papers Published in Journals and Conferences

AS FIRST AUTHOR
Year International Journal International Conferences National Conferences Total
2006 NIL 01 03 04
2007 NIL 05 01 06
2008 06 08 02 16
2009 02 NIL NIL 02
2010 01 NIL NIL 01
AS CO-AUTHOR
2006 NIL 01 02 03
2007 06 10 01 17
2008 02 16 05 23
2009 01 02 NIL 03
2010 03 05 NIL 08
TOTAL 21 49 15 85

AWARDS

Best Student Paper Award

National Conference on Trends in VLSI and Embedded System, Indian Microelectronics Society (IMS-2007), Punjab Engineering College Chandigarh, India, pp.33-37, August 17-18, 2007.


RECESSED CHANNEL MOSFET

International Journals:

  1.  “Design Considerations and Impact of Technological Parametric Variations on RF/Microwave Performance of GEWE-RC MOSFET”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Microwave and Optical Technology Letters, Vol.52, No.3, pp.652-657, 2010.
  2.  “Gate Material Engineered-Trapezoidal Recessed Channel MOSFET (GME-TRC) for High Performance Analog and RF Applications”, Priyanka Malik, Sona P.Kumar, Rishu Chaujar, Mridula Gupta and R. S. Gupta, Microwave and Optical Technology Vol.52, No.3, pp.694-698, 2010.
  3.  “TCAD assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its multi-layered gate architecture, Part II: Analog and large signal performance evaluation”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Superlattices and Microstructures, Volume 46, Issue 4, Pages 645-655, October 2009.
  4.  “Two-dimensional threshold voltage model and design considerations for gate electrode work function engineered recessed channel nanoscale MOSFET: I”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Semiconductor Science and Technology, Vol.24, 10pp, 2009.
  5.  “TCAD Assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its Multi-Layered Gate Architecture: Part-I: Hot Carrier Reliability Evaluation”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, IEEE Transactions on Electron Devices, Vol.55, No.10, pp. 2602-2613, October, 2008.
  6.  “Laterally amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET For ULSI”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Microelectronic Engineering, Vol. 85, No. 3, pp. 566-576, March 2008.
  7.  “Two-Dimensional Analytical Sub-Threshold Model of Multi-Layered Gate Dielectric Recessed Channel (MLaG-RC) Nanoscale MOSFET”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Semiconductor Science and Technology, Vol.23, No.4, April, 2008.
  8.  “Intermodulation Distortion and Linearity Performance Assessment of 50-nm gate length L-DUMGAC MOSFET for RFIC Design”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Superlattices and Microstructures, Vol.44, pp.143-152, 2008.
  9.  “Investigation of Multi-Layered-Gate Electrode Workfunction Engineered Recessed Channel (MLGEWE-RC) Sub-50nm MOSFET: A Novel Design”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, International Journal of Numerical Modeling: Electronic Networks, Devices and Fields (Accepted July 2008).
  10.  “On-State and RF Performance Investigation of Sub-50nm L-DUMGAC MOSFET Design for High-Speed Logic and Switching Applications”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Semiconductor Science and Technology, Vol.23, No.9, September, 2008.

International Conferences:

  1.  “Exploration of the Effect of Negative Junction Depth on the Electrical Characteristics of Concave DMG MOSFET in Sub-50-Nanometer Regime”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, International Conference on Computers and Devices for Communication (CODEC-2006), Institute of Radio physics and Electronics, University of Calcutta, pp. 317-319, December 18-20, 2006.
  2.  “RF-Distortion in Sub-100nm L-DUMGAC MOSFET”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007), Mumbai, pp.168-170, December 16-20, 2007.
  3.  “Two-Dimensional Analytical Threshold Voltage Model for Nanoscale SG-Concave MOSFET in Sub-50nm Regime”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007), Mumbai, pp.221-224, December 16-20, 2007.
  4.  “Pre-Distortion Linearity Enhancement for Sub-50nm Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, International Symposium on Microwave and Optical Technology (ISMOT 2007), Villa Mondragone, Monte Porzio Catone, Italy, pp.797-800, 17-21 December 2007.
  5.  “On-State and Switching Performance Investigation of Sub-50nm L-DUMGAC MOSFET Design for High-Speed Logic Applications”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, International Semiconductor Device Research Symposium (ISDRS 2007), University of Maryland, USA,pp.1892-1893, December 12-14, 2007.
  6.  “Two-Dimensional Analytical Modeling and Simulation of Rectangular Gate Recessed Channel (RG-RC) Nanoscale MOSFET in Sub-50nm Regime”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Indo-Australian Symposium on Multifunctional Nanomaterials, Nanostructures and Applications (MNNA 2007), pp.110, December 19–21, 2007, New Delhi, India.
  7.  “Sub-Threshold Drain Current Performance Assessment of MLGEWE-RC MOSFET for CMOS Technology”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, IEEE Sponsored Mini Colloquia on Compact Modeling of Advance MOSFET Structures and Mixed Mode Applications-2008, pp. 27-28, January 5-6 2008, South Campus, Delhi University, New Delhi, India.
  8.  “RF Performance Assessment of L-DUMGAC MOSFET for Future CMOS Technology in GigaHertz Regime”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, IEEE Sponsored Mini Colloquia on Compact Modeling of Advance MOSFET Structures and Mixed Mode Applications-2008, pp. 29-30, January 5-6 2008, South Campus, Delhi University, New Delhi, India.
  9.  “TCAD Investigation of Hot Carrier Reliability Issues Associated with GEWE-RC MOSFET”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, 2nd IEEE International Nanoelectronics Conference (INEC-2008), pp.1434-1437, March 24-27, 2008, Shanghai, China.
  10.  “Compact Analytical Threshold Voltage Model for Nanoscale Multi-Layered-Gate Electrode Workfunction Engineered Recessed Channel (MLGEWE-RC) MOSFET”, R.Chaujar, R.Kaur, M.Saxena, M.Gupta and R. S. Gupta, 2008 Workshop on Compact Modeling (WCM-2008), pp.873-876, June 1-5, 2008, Boston, Massachusetts, U.S.A.
  11.  “Assessment of L-DUMGAC MOSFET for High Performance RF Applications with Intrinsic Delay and Stability as Design Tools”, R.Chaujar, R.Kaur, M.Saxena, M.Gupta and R. S. Gupta, 11th International Conference on Modeling and Simulation of Microsystems (MSM-2008), pp.586-589, June 1-5, 2008, Boston, Massachusetts, U.S.A.
  12.  “Impact of Multi-Layered Gate Design on Hot Carrier Reliability of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET”, R.Chaujar, R.Kaur, M.Saxena, M.Gupta and R. S. Gupta, XXIX General Assembly of the International Union of Radio Science (Union Radio Scientifique Internationale-URSI), Illinois, USA, August 07-16, 2008.
  13.  “GEWE-RC MOSFET: A Solution to CMOS Technology for RFIC Design Based on the concept of Intercept Point”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S.Gupta, International Conference on Recent Advancements in Microwave Theory and Applications (Microwave-2008), pp.661-663, Jaipur, India, November 21-24, 2008.
  14.  “GEWE-RC MOSFET: High Performance RF Solution to CMOS Technology”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S.Gupta, Asia Pacific Microwave Conference (APMC-2008), December 16-19, 2008, Hongkong, China.
  15.  “Evaluation of Multi-Layered Gate Design on GEWE-RC MOSFET for Wireless Applications in terms of Linearity-Distortion Issues”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S.Gupta, International Symposium on Microwave and Optical Technology (ISMOT 2009), December 16-19, New Delhi, India. (Accepted September 2009).
  16.  “Exploring the effect of Negative Junction Depth on Electrical Behaviour of Sub-50nm GME-TRC MOSFET: A Simulation Study”, Priyanka Malik, Rishu Chaujar, Mridula Gupta and R.S.Gupta,, International Conference On Recent Advancements in Microwave Theory and Applications (Microwave-2008), November 21-24, 2008, Jaipur, India (Accepted August 2008).
  17.  “Gate Material Engineered-Trapezoidal Recessed Channel MOSFET (GME-TRC) for Ultra Large Scale Integration (ULSI)”, Priyanka Malik, Sona P.Kumar, Rishu Chaujar, Mridula Gupta and R.S.Gupta, Asia Pacific Microwave Conference (APMC-2008), December 16-19, 2008, Hongkong, China (Accepted September 2008).
  18.  “Two-Dimensional Analytical Model for Trapezoidal Recessed Channel (TRC) MOSFET using Gate Material Engineering”, Priyanka Malik, Rishu Chaujar, Mridula Gupta and R.S.Gupta, International Symposium on Microwave and Optical Technology (ISMOT 2009), December 16-19, New Delhi, India. (Accepted September 2009).

National Conferences:

  1.  “Exploring the Effect of Negative Junction Depth on Electrical Behaviour of Sub-50-Nanometer Concave DMG MOSFET: A Simulation Study”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, National Conference on Recent Advancement in Microwave Technique and Applications (Microwave-2006), pp. 123-125, 6-8 October 2006, Jaipur, India.
  2.  “New Concave MOSFET with Transverse Dual Material Gate (T-DMG) in Sub-50nm Regime: A Simulation Study", Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, National Conference on Trends in VLSI and Embedded System (IMS-2007), pp.33-37, August 17-18, 2007, Punjab Engineering College, Chandigarh, India.
  3.  “Solution to CMOS Technology for High Performance Analog Applications: GEWE-RC MOSFET”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, National Conference on Advanced Optoelectronic Materials and Devices (AOMD 2008), 22-24 December 2008, IT-BHU, Varanasi, India (Accepted November 2008).
  4.  “Effect of control gate length on Device Performance of GME-TRC MOSFET”, P.Malik, S.P.Kumar, R.Chaujar, M.Gupta and R.S Gupta, National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2008), pp.309-312, 26-28 September 2008, New Delhi, India.
  5. “Effect of control gate length on Device Performance of GME-TRC MOSFET”, P.Malik, R.Chaujar, M.Gupta and R.S Gupta, National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2010), pp.309-312, 30-31 January 2010, New Delhi, India.

INSULATED SHALLOW EXTENSION MOSFET

International Journals:

  1.  “Performance Investigation of 50nm Insulated Shallow Extension Gate Stack (ISEGaS) MOSFET for Mixed Mode Applications,” Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, IEEE Transactions on Electron Devices, Vol. 54, No.2, pp. 365-368, February 2007.
  2.  “Unified Subthreshold Model for Channel Engineered Sub-100nm Advanced MOSFET Structures”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, IEEE Transactions on Electron Devices, Vol.54, No.9, pp.2475-2486, September 2007.
  3.  “Hot carrier reliability and analog performance investigation of DMG-ISEGaS MOSFET”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, IEEE Transactions on Electron Devices, Vol. 54, No.9, pp.2556-2561, September 2007.
  4.  “Two-Dimensional Analytical Model to Characterize Novel MOSFET Architecture: Insulated Shallow Extension (ISE) MOSFET”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, Semiconductor Science and Technology, Vol.22,No.8, pp.952-962, August 2007.
  5.  “Lateral Channel Engineered - Hetero Material Insulated Shallow Extension Gate Stack (HMISEGAS) MOSFET Structure: High Performance RF Solution for MOS Technology ”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, Semiconductor Science and Technology, Vol.22, No.10, pp. 1097-1103, October 2007.
  6.  “Two-Dimensional Analytical Modeling and Simulation of a Novel Gate-Stack ISE MOSFET”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Microelectronic Engineering, Vol.86, pp.2005-2014, 2009.
  7.  “Hot Carrier Reliability Monitoring of DMG ISE SON MOSFET for Improved Analog Performance”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, Microwave and Optical Technology Letters, Vol.52, No.3, pp. 770-775, 2010.

International Conferences:

  1.  “Gate Oxide Engineered Dual Material Gate Insulated Shallow Extension (GOXDMG-ISE) MOSFET: A New Vent to Wireless Communication”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, 3rd International Conference on Computers and Devices for Communication (CODEC-2006), Institute of Radio physics and Electronics, university of Calcutta, pp. 324-327, December 18-20, 2006.
  2.  “Nanoscale Insulated Shallow Extension MOSFET with Dual Material Gate for High Performance Analog Operations” , Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007), Mumbai, pp.171-173, December 16-20, 2007.
  3.  “Sub-Threshold Performance Consideration of a Novel Architecture: ISEGaS deca-nanometer MOSFET”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007), Mumbai, pp.123-126, December 16-20, 2007.
  4.  “Linearity Assessment in DMG ISEGaS MOSFET for RFIC Design”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Asia Pacific Microwave Conference (APMC-2007), pp.2495-2498, December 11-14, 2007, Bangkok, Thailand.
  5.  “Electrical Characterization of Insulated Shallow Extension (ISE) MOSFET: A Punchthrough Stopper”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, International Symposium on Microwave and Optical Technology (ISMOT 2007), Villa Mondragone, Monte Porzio Catone, Italy, pp.813-816, 17-21 December 2007.
  6.  “Dual Material Gate (DMG) SOI-MOSFET with Dielectric Pockets: Innovative Sub-50 nm design for improved switching performance”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, Indo-Australian Symposium on Multifunctional Nanomaterials, Nanostructures and Applications (MNNA 2007), pp.109, December 19–21, 2007, New Delhi, India.
  7.  “TCAD Investigation of a Novel MOSFET Architecture of DMG ISE SON MOSFET for ULSI Era”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, IEEE Sponsored Mini Colloquia on Compact Modeling of Advance MOSFET Structures and Mixed Mode Applications-2008, pp. 18-19, January 5-6 2008, South Campus, Delhi University, New Delhi, India.
  8.  “Analytical Analysis of Sub-Threshold Performance of Sub-100nm Advanced MOSFET Structures-An Iterative Approach”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, IEEE Sponsored Mini Colloquia on Compact Modeling of Advance MOSFET Structures and Mixed Mode Applications-2008, pp. 20-21, January 5-6 2008, South Campus, Delhi University, New Delhi, India.
  9.  “Nanoscale Analytical Modeling and TCAD Simulation SDPI MOSFET”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, 2nd IEEE International Nanoelectronics Conference (INEC-2008), pp. 964-969, March 24-27, 2008, Shanghai, China.
  10.   “Pre-Distortion Assessment of Workfunction Engineered Multi-Layer Dielectric Design of DMG ISE SON MOSFET”, R.Kaur, R.Chaujar, M.Saxena and R. S. Gupta, 11th International Conference on Modeling and Simulation of Microsystems (MSM-2008), pp.605-606, June 1-5, 2008, Boston, Massachusetts, U.S.A.
  11.  “An Iterative Approach to Characterize Various Advanced Non-Uniformly Doped Channel Profiles”, R.Kaur, R.Chaujar, M.Saxena and R. S. Gupta, 2008 Workshop on Compact Modeling (WCM-2008), pp.814-817, June 1-5, 2008, Boston, Massachusetts, U.S.A.
  12.  “Impact of Gate Stack Configuration onto the RF/analog Performance of ISE MOSFET”, R.Kaur, R.Chaujar, M.Saxena, and R. S. Gupta, International Conference On Recent Advancements in Microwave Theory and Applications (Microwave-2008), November 21-24, 2008, Jaipur, India (Accepted August 2008).
  13.  “TCAD Performance Investigation of a Novel MOSFET Architecture of Dual Material Gate Insulated Shallow Extension Silicon On Nothing (DMG ISE SON) MOSFET for ULSI Era”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R.S.Gupta, Asia Pacific Microwave Conference (APMC-2008), December 16-19, 2008, Hongkong, China (Accepted September 2008).
  14.  “Analytical Drain Current Evaluation Technique for Various Non-Uniformly Doped MOS Device Architectures”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R.S. Gupta, International Symposium on Microwave and Optical Technology (ISMOT)-2009 to be held during December 16-19,2009 in Hotel Ashok, New Delhi, India (Accepted)

National Conferences:

  1.  “RF Performance Investigation of Gate Stacked Insulated Shallow Extension (ISE) MOSFET and Bulk: A Comparative Study,” Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2006), pp 254-258, 24-26 March 2006, New Delhi, India.
  2.  “Lateral Channel Engineered Structure- Insulated Shallow Extension (ISE) MOSFET: DC and RF Performance Investigation”, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, National Conference on Recent Advancement in Microwave Technique and Applications (Microwave-2006), pp. 119-122, 6-8 October 2006, Jaipur, India.
  3.  “Effect of transport property on the performance of insulated shallow extension gate stack (ISEGaS) MOSFET", Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, National Conference on Trends in VLSI and Embedded System (IMS-2007), pp.52-57, August 17-18, 2007, Punjab Engineering College, Chandigarh, India.
  4.  “Simulation of a Novel ISE MOSFET with Gate Stack Configuration”, R.Kaur, R.Chaujar, M.Saxena and R.S Gupta, National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2008), pp.291-296, 26-28 September 2008, New Delhi, India.


ALGaN/GaN HIGH ELECTRON MOBILITY TRANSISTOR

International Journals:

  1.  “Threshold Voltage Model for Small Geometry AlGaN/GaN HEMTs Based on Analytical Solution of 3-D Poisson’s Equation,” Sona P.Kumar, Anju Agrawal, Rishu Chaujar, Sneha Kabra, Mridula Gupta and R. S. Gupta, Microelectronics Journal, Vol.38, No.10-11, pp.1013-1020, October-November 2007.
  2.  “Analytical Modeling and Simulation of Subthreshold Behavior in Nanoscale Dual Material Gate AlGaN/GaN HEMT”, Sona P.Kumar, Anju Agrawal, Rishu Chaujar, Mridula Gupta and R. S. Gupta, Superlattices and Microstructures, Vol.44, pp.37-53, July, 2008.
  3.  “Performance Assessment and Sub-Threshold Analysis of Gate Material Engineered AlGaN/GaN HEMT For Enhanced Carrier Transport Efficiency”, Sona P.Kumar, Anju Agrawal, Rishu Chaujar, Mridula Gupta and R. S. Gupta, Microelectronics Journal, Vol.39, No.12, pp.1416-1424, December, 2008.

International Conferences:

  1.  “3-Dimensional Analytical Modeling and Simulation of Fully Depleted AlGaN/GaN Modulation Doped Field Effect transistor”, Sona P.Kumar, Anju Agrawal, Rishu Chaujar, Sneha Kabra, Mridula Gupta and R. S. Gupta, Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007), pp.373-376, December 16-20, 2007, Mumbai, India.
  2.  “Analytical Modeling and Simulation of Potential and Electric Field Distribution in Dual Material Gate HEMT For Suppressed Short Channel Effects”, Sona P.Kumar, Anju Agrawal, Rishu Chaujar, Mridula Gupta and R. S. Gupta, Asia Pacific Microwave Conference (APMC-2007), pp.2503-2506, December 11-14, 2007, Bangkok, Thailand.
  3.  “Analytical Modeling and Simulation of Small Geometry AlGaN/GaN HEMTs”, Sona P.Kumar, Anju Agrawal, Rishu Chaujar, Sneha Kabra, Mridula Gupta and R. S. Gupta, International Symposium on Microwave and Optical Technology (ISMOT 2007), Villa Mondragone, Monte Porzio Catone, Italy, pp.279-282, 17-21 December 2007.
  4.   “Two-Dimensional Analytical Sub-Threshold Modeling and Simulation of Gate Material Engineered HEMT For Enhanced Carrier Transport Efficiency”, Sona P.Kumar, Anju Agrawal, Rishu Chaujar, Mridula Gupta and R. S. Gupta, International Semiconductor Device Research Symposium (ISDRS 2007), University of Maryland, USA,pp.1892-1893, December 12-14, 2007.
  5.   “Impact of GME Design on Nanometer HEMT Capacitances and its Influence on Device RF Performance”, Sona P.Kumar, Anju Agrawal, Rishu Chaujar, Mridula Gupta and R. S. Gupta, IEEE Sponsored Mini Colloquia on Compact Modeling of Advance MOSFET Structures and Mixed Mode Applications-2008, pp. 31-32, January 5-6 2008, South Campus, Delhi University, New Delhi, India.
  6.  “Nanoscale HEMT with GME Design for High Performance Analog Applications”, Sona P.Kumar, Anju Agrawal, Rishu Chaujar, Mridula Gupta and R. S. Gupta, IEEE Sponsored Mini Colloquia on Compact Modeling of Advance MOSFET Structures and Mixed Mode Applications-2008, pp. 33-34, January 5-6 2008, South Campus, Delhi University, New Delhi, India.
  7.  “Linearity Performance Enhancement of DMG AlGaN/GaN High Electron Mobility Transistor”, S.P.Kumar, A.Agrawal, R.Chaujar, M.Gupta and R. S. Gupta, 11th International Conference on Modeling and Simulation of Microsystems (MSM-2008), pp.607-610, June 1-5, 2008, Boston, Massachusetts, U.S.A.
  8.  “Investigating the Linearity Performance of DMG AlGaN/GaN HEMT for Improved RF Applications”, Sona P.Kumar, Anju Agrawal, Rishu Chaujar, Mridula Gupta and R. S. Gupta, XXIX General Assembly of the International Union of Radio Science (Union Radio Scientifique Internationale-URSI), Illinois, USA, August 07-16, 2008. (Accepted May 2008).
  9.  “RF Performance Investigation of DMG AlGaN/GaN High Electron Mobility Transistor”, Sona P.Kumar, Anju Agrawal, Rishu Chaujar, Mridula Gupta and R. S. Gupta, International Conference On Recent Advancements in Microwave Theory and Applications (Microwave-2008), November 21-24, 2008, Jaipur, India (Accepted August 2008).
  10.  “DMG AlGaN/GaN HEMT: A Solution to RF and Wireless Applications for Reduced Distortion Performance”, Sona P.Kumar, Anju Agrawal, Rishu Chaujar, Mridula Gupta and R. S. Gupta, Asia Pacific Microwave Conference (APMC-2008), December 16-19, 2008, Hongkong, China (Accepted September 2008).

National Conferences:

  1.  “Impact of Dual Material Gate Design on AlGaN/GaN High Electron Mobility Transistor’s RF Performance” S.P.Kumar, A.Agrawal, R.Chaujar, M.Gupta and R.S.Gupta, National Conference Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2008), pp.313-316, 26-28 September, New Delhi, India.


FIELD PROGRAMMABLE GATE ARRAY (FPGA)

National Conferences:

  1.  “Design and FPGA realization of Direct Sequence-Spread Spectrum (DS-SS) BPSK Modulator using a Five Stage Gold Code Generator”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena and R. S. Gupta, National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2006), pp 213-216, 24-26 March 2006, New Delhi, India.
  2.  “Scrambled Sequence FPGA based Direct Sequence Spread Spectrum BPSK Modulator: 10 Stage Analysis”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta National Conference on Recent Trends in Electronics and Information Technology, (RTEIT 2006) ,pp 334-337, 28-29 July 2006, Kopargaon Maharashtra, India.
  3.  “Development Board-Level Experimentation and Simulation of FPGA based DEBPSK DSSS Modulator: Implementation of 10-Chip Gold Code Sequence Generator”, Rishu Chaujar, Ravneet Kaur, Manoj Saxena and R. S. Gupta, National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2008), pp.255-261, 26-28 September 2008, New Delhi, India.

MISCELLANEOUS

International Conferences:

  1.  “Two Dimensional Analytical Modeling of Multi-Layered Dielectric G4 MOSFET-A Novel Design”, R.S.Gupta, N.Sharma, J.Bansal, R.Chaujar and M.Gupta, International Conference On Recent Advancements in Microwave Theory and Applications (Microwave-2008), November 21-24, 2008, Jaipur, India (Invited Talk).
  2.  “Two-Dimensional Analytical Sub-Threshold Model Of Double Gate MOSFET With Gate Stack”, J.Bansal, N.Sharma, S.P.Kumar, R.Chaujar, M.Gupta and R.S Gupta, International Conference On Recent Advancements in Microwave Theory and Applications (Microwave-2008), November 21-24, 2008, Jaipur, India (Accepted August 2008).

National Conferences:

  1.  “Analytical Modeling of Multi-Layered Dielectric G4-MOSFET for Improved Short Channel Effects”, N.Sharma, J.Bansal, S.P.Kumar, R.Chaujar, M.Gupta and R.S Gupta, National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2008), pp.317-320, 26-28 September 2008, New Delhi, India.
  2.  “Experimental Investigation of Emergency Siren Simulator for Real-Time Small-Signal Power Applications”, Prince, Rajat, Anju Agrawal, Rishu Chaujar, Ravneet Kaur, National Conference on Advanced Optoelectronic Materials and Devices (AOMD 2008), 22-24 December 2008, IT-BHU, Varanasi, India (Accepted November 2008).
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